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watch
- 功能更强大的数字时钟,有年份,月,日,时,分,秒和星期,可以调校-More powerful digital clock, there are years, months, days, hours, minutes, seconds and weeks, you can adjust the
sheji2
- 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
clock
- 本文档采用VHDL语言编写了一个数字时钟的程序，该数字时钟采用24小时制计时，可以实现整点报时，时间设置，闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clo
digital_clock
- 一个关于数字时钟设计实现的VHDL源代码，已测试过，可以运行-Design and implementation of a digital clock on the VHDL source code has been tested, you can run
eda
- eda实验时钟电路系统由秒时钟产生电路、走时电路模块、数字显示模块、校时模块、语音报时模块、工业控制模块-eda test clock circuit generated by the second clock circuit, the circuit blocks away, the digital display module, the campus module, voice timekeeping module, industrial control modules
VerilogHDL
- vhdl多功能数字钟数字钟是一种用数字电路技术实现时、分、秒计时的装置，与机械式时钟相比具有更高的准确性和直观性-vhdl multifunction digital clock digital clock is a digital circuit technology with the hours, minutes, seconds, timing devices, and mechanical clock higher than the accuracy and intuitive
clock
- 用vhdl写的数字电子时钟，能够定闹钟，定点报时，调时，用Quartus II 7.2 (32-Bit)写的，压缩文件，里面有源程序，仿真文件等（就是所建的工程）-Digital electronic clock vhdl write, to set the alarm clock, designated chime tune, written using Quartus II 7.2 (32-Bit), compressed files, source code and simulation
EDA_VHDL_shuzizhong
- EDA课程设计实验VHDL硬件描述语言实现数字时钟-EDA curriculum design experiments VHDL hardware descr iption language digital clock
time-project
- 用VHDL语言实现数字时钟显示、控制、复位、加减、按键消抖-Using VHDL digital clock display, control, reset, subtraction, key debounce etc.
shuzipinlvji
- 1.用VHDL完成12位十进制数字频率计的设计及仿真。 2.频率测量范围：1Hz～10KHz，分成两个频段，即1～999Hz，1KHz～10KHz，用三位数码管显示测量频率，用LED显示表示单位，如亮绿灯表示Hz，亮红灯表示KHz。 3.具有自动校验和测量两种功能，即能用标准时钟校验、测量精度。 4.具有超量程报警功能，在超出目前量程档的测量范围时，发出灯光和音响信号。 -1 completed 12 with VHDL design and simulation of d
VHDL
- 数字时钟，实现24小时数码管显示，可以实现按键校时-Digital clock, 24 hours to achieve digital display, you can achieve the key school
shuzhishizhong
- 数字时钟的verilog程序,课程设计，数字电子技术实验，VHDL-VHDL Verilog.
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
数字时钟
- 基于VHDL语言编写的数字时钟程序，经验证，可以用硬件实现(Based on VHDL language digital clock program, verified, you can use hardware to achieve.)