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jiaotongdeng
- 这程序是利用状态机来控制交通灯verilog码-This procedure is the use of state machine to control the traffic lights verilog code
c73a2ceb-09a5-4366-83ea-78b08c6200eb
- jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true
IOcontrol
- 输入输出控制的状态机，verilog HDL源码-Input and output control state machine, verilog HDL source
Verilog
- 交通灯状态机设计的完整Verilog代码-Verilog
serial_in
- verilog 串并转换程序 状态机 有4位前导码 共转换3位 可自己修改后转换更多的串行数据位-Verilog serial signal to parallel signal transfer
state-machine-program
- Verilog三段式状态机.pdf Verilog时序电路及状态机设计.ppt Verilog有限状态机设计.ppt 状态机.ppt 用状态机原理进行软件设计.pdf 有限状态机.pdf 有限状态机.ppt 状态机原理及用法.pdf 对状态机初学者有帮助。 -Verilog three-state machine the pdf Verilog Sequential Circuits and the state machine design. Ppt Veri
paomadeng2
- 简单的跑马灯verilog程序，笔者是初学者，利用简单状态机编写的-Simple Marquee verilog program, the author is a beginner, use a simple state machine to write
AD9854verilog
- verilog 编写的AD9854配置代码 通过状态机转换来配置AD9854-CONGIURE the ad9854 dds
Traffic
- 交通灯控制器的Verilog代码，采用了三段式的状态机描述，适合学习和练习，包括了验证代码-A Verilog code of Traffic light controller, using a three-stage state machine descr iption suitable for learning and practice, including the verification code
verilog
- 一些基本的Verilog 代码 包括基本的分频器设计，交通灯设计，自动售货机设计，有限状态机的设计-Some basic Verilog For freshman
verilog_iic_at24c04
- verilog语言实现的iic协议通信，一段式状态机实现，结合按键和数码管，用来控制和显示数据-Verilog language the iic protocol communication, for some state machine implementation, buttons and digital tube, used to control and display data.
key
- verilog的按键消抖程序，利用状态机完成的-verilog the the key debounce program, the completion of the state machine
cache
- 基于MIPS思维方式，verilog语言，简单的cache 控制器设计，状态机共分4个状态，同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
traffic
- 基于Verilog的交通灯，包含分频器模块、计数模块以及控制模块。状态机编写-Verilog-based traffic lights, including the divider block, counting module and a control module. Write state machine
xvlijiance
- 附件包括四个内容1.采用Verilog编写的状态机实现序列检测的ISE工程2.代码文档一份3.原理说明4.使用说明。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Accessories include four content of 1 by the state machine Verilog prepared realize sequence detection ISE works 2 code document a 3 principle that 4 instructi
NandBuffer
- verilog编写，含三路正弦信号发生器，三路数据乒乓缓存模块。乒乓缓存读写控制采用三段式状态机实现。-The project contains a 3-channel sine generator and a 3-channel ping-pong buffer which is written in verilog. The write and read control of buffer is implemented in 3-segment FSM.
class8_FSM
- 序列检测机（状态机实验），是Verilog状态机最基本的小实验，用于体会状态机的原理和作用（原作者：小梅哥）(Sequence detection machine is the most basic small experiment of Verilog state machine)
fsm3
- verilog状态机实验，说明一个状态机的生成过程(Verilog state machine experiment, which illustrates the generation process of a state machine)
new.v
- 状态机写的axi slave，模式较少，基本功能齐全，轻便,仿真综合通过(AXI4 slave programmed by state machine approach)