8位二进制数乘法器VHDL实现8位二进制数乘法器设计，乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from the least significant bit of