搜索资源列表
RTC
- verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等-verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other
lab1
- apb transactions with DUT, testbench including interface test cases , top
apb_uart_sv-pulpinov1
- SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
AXI&APB2SPI
- APB总线转SPI接口模块SV代码以及AXI总线转SPI接口模块SV代码(SV code of APB bus to SPI interface module and SV code of Axi bus to SPI interface module)