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EP1C3_12_7_SPCTR
- 基于FPGA的信号采集及频谱分析,用VHDL编写,压缩包里是Quartus下的工程。AD采样用状态机实现,并存入LPM_RAM。设计了一个UART模块(也是状态机实现的),可将数据发到PC机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
uart2
- PC机上开串口调试助手,发送一个字符到开发板(中间通过串口线相连) FPGA收到字符后,回发给PC机上,在串口助手上显示-PC, open the serial debugging assistant to send a character to the development board (the middle through the serial line connected) FPGA received after the character, and posted back to t
usb_ctl
- CH372 USB芯片 采用Verilog语言,实现FPGA与上位机通信,按键触发FPGA向上位机传数,USB测试软件向FPGA传数-CH372 USB chip using Verilog language, to achieve FPGA and PC communications, key trigger FPGA pass up crew numbers, USB test software to pass several FPGA
chuankou
- 实现FPGA与PC的串口通信,工程文件完整,可直接运行,VHDL代码-FPGA implementation of serial communication with the PC, complete engineering documents, can be directly run, VHDL code
111
- FPGA 实现全双工异步串口(UART),与PC 机通信。1 位起始位;8 位数据位;一个停止位;无校验位;波特率为2400、4800、9600、11520 任选或可变(可用按键控制波特率模式)-FPGA to achieve full-duplex asynchronous serial interface (UART), to communicate with the PC. A start bit 8 data bits one stop bit no parity bit 240
uart_ps2
- ps2接口的verilog module 负责用键盘发送数据,附带仿真task仿真,代码简单明了。 uart接口的verilog module ,通过PC机上的串口助手接收并显示键盘发送的数据 FPGA 板调试OK-ps2 verilog module with uart verilog module,fpga simulation ok.ps2 send data and uart get data and display in PC
USB3_a3p1000_9.1__
- 8bit10bit编解码、SPI解串、BAT656接受源码,并通过USB3.0 传送至PC机。经测试actel fpga 时钟频率100M可以满足320MB/s的传输速率-8bit10bit encoding and decoding, SPI solution string, BAT656 accept the source code, and through USB3.0 to PC. After testing the FPGA Actel clock frequency 100M can
uart_2_pc
- 实现FPGA和PC通过串口传输数据,已经通过验证,可以结合自己的设计直接拿来用(ealize FPGA and PC to transmit data through serial port)
基于FPGA与PC串口自收发通信-Verilog
- 基于FPGA与PC串口自收发通信-Verilog(Self-transceiving Communication Based on FPGA and PC Serial Port-Verilog)