搜索资源列表
Pro_19
- Fpga,DDS,PLL,rom(正弦波)(f<13MHz,需要滤波)(Verilog)-Fpga, DDS, PLL, rom
4BIT_COUNTER
- 4-bit counter which counts from 0 to 16. This logic has got one PLL needs to be regenerated based on the FPGA vendor.
PLL
- 在FPGA里加入时钟锁相环，输出多种时钟，最后用modelsim对源代码进行了仿真处理；-Join clock PLL simulation