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DIVCLK
- 该程序是用VHDL语言实现的时钟分频程序，可以把高频时钟信号分成低频时钟信号，便于实际应用。-The program is the realization of VHDL language program the clock frequency, high frequency clock signal can be divided into low-frequency clock signal, to facilitate the practical application.
CLOK
- 时钟分频。使用原有高频信号，将其10倍频，得到可用于八段数码管显示的扫描信号-Clock frequency. The use of the original high-frequency signal, frequency-doubling of its 10, the eight can be used to display the scanned digital signal
fenpin27
- VHDL硬件语言系统时钟27分频程序，可用于各种时钟分频参考-VHDL hardware language system clock frequency of the program, 27 points can be used for a variety of clock divider reference
clkNdiv
- 很经典的时钟分频代码，直接拿来可以使用 使用VHDL语言编写！-Very classic clock divider code can be directly used to use using VHDL language!
shizhong
- VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。-verilog HDL
example
- 基于VHDL的简单时钟分频程序（可自行更改分频系数）-simple frequency