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基于VHDL的CPU程序
- 可实现加 减 与 或 非 移位功能的用vhdl语言编写可仿真的CPU程序
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
Jh_cpu
- Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
cpu
- 基于MIPS指令集的32位CPU设计与VHDL实现-Based on the MIPS instruction set of the 32-bit CPU design and the realization of VHDL
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
VHDL
- 基于VHDL设计的通用实验CPU中译码器部分，用于进行指令译码。-VHDL design of experiments based on general-purpose CPU in the decoder part, used for instruction decoding.
cpu
- 简单CPU 能处理10条简单CPU指令 不包括IO指令-Simple CPU can process 10 a simple CPU instructions do not include IO commands
WatchForLab
- This was the first lab assigmnet in the course CPU Architecture, creat a basic watch
computerc
- VHDL 编写的简单的CPU 输入程序可以进行有优先级的加减与或的计算，包含键盘和数码管的程序-CPU write simple VHDL program can enter a priority level or the calculation of addition and subtraction and that contains the keyboard and digital control of the process
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
Plasma_Cpu_r10.tar
- Plasma CPU: VGA coded with C and VHDL in Xilinx FPGA
CPU_project
- CPU设计与实践实验源码，工程文件 ise。VHDL代码 可直接运行-cpu project
CPU
- 使用vhdl实现一个简易的cpu包含and or xor add sub mul 指令-Achieved using a simple vhdl cpu contain and or xor add sub mul instruction
CPU1
- 一个简单的多周期的基于MIPS的CPU设计-cpu VHDL
CPU
- 计算机组织与结构课程设计，使用VHDL设计一个简单功能的CPU。该CPU拥有基本的指令集，并且能够使用指令集运行简单的程序。另外，CPU的控制器部分（CU）采用微程序设计方式。-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to g
lab03-.tar
- vhdl about 3 stage control block of cpu-vhdl control block of the 3 stage cpu(FSM)
VHDL
- 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计- Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
cpu2
- 基于vhdl语言的cpu模拟，包含仿真，含所有器件(CPU containing simulation based on VHDL language)