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jishuqi.rar
- 描述的是一个带有异步复位和同步时钟使能的十进制加法计算器,,With reset and clock enable decimal calculator
VHDL
- 1、 设计一个简易电子琴。要求能演奏的音域为中音的 1 到高音的 1。 2、 用GW48－PK2中的8个按键作为琴键。 3、 GW48－PK2中有扬声器。 4、 可以使用GW48－PK2上的12MHz作为输入时钟信号。 -1, the design of a simple flower. Requirements can play for the tenor of the range of 1 to treble the 1.2, and GW48-PK2 in eight ke
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
shizhong
- 用vhdl语言描述时钟的功能，并通过七段译码显示输出。-VHDL language used to describe the function of the clock and through the Seven-Segment display decoder output.
watch
- 功能更强大的数字时钟,有年份,月,日,时,分,秒和星期,可以调校-More powerful digital clock, there are years, months, days, hours, minutes, seconds and weeks, you can adjust the
clock
- 电子时钟具有一般时钟所具有的所有功能，定时，报时，显示时间和日期以及秒表等等功能。-electric clock
clock
- 60进制计数器，采用十分简便的方法，能够很快速的完成计数功能。-60 M-ary counter, using a very simple way to very quickly complete the count function.
sdram_vhdl_lattice
- sdram的控制程序，程序分为控制端口模块、时钟模块、数据传输模块及刷新等模块-sdram control procedures, process control port is divided into modules, clock modules, data transfer module and refresh modules
sheji2
- 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
EDA
- 以前学EDA的时候做过的四个小程序，分别是24/12小时制数字钟、数字频率计、乐曲播放电路、多人智力竞赛抢答器-EDA previously done when the four small procedures are 24/12 hour digital clock, digital frequency meter, circuit music players and many more devices quiz Answer
spi.tar
- This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
clock
- 本文档采用VHDL语言编写了一个数字时钟的程序，该数字时钟采用24小时制计时，可以实现整点报时，时间设置，闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clo
clock
- 电子时钟，能够进行计时，可设定闹钟，可以当做跑表，并且可以更改时间-electric clock
CLOK
- 时钟分频。使用原有高频信号，将其10倍频，得到可用于八段数码管显示的扫描信号-Clock frequency. The use of the original high-frequency signal, frequency-doubling of its 10, the eight can be used to display the scanned digital signal
uart_test_ok_921
- 一个简单的uart 源码，接收一个字符并发回，通过测试，可以使用的，输入时钟12mhz,发送速率96-A simple uart source code, receiving a character and send back through the test, can be used, input clock 12mhz, sending rate 9600
clock
- a vhdl code for digital clock
clock
- 用vhdl写的数字电子时钟，能够定闹钟，定点报时，调时，用Quartus II 7.2 (32-Bit)写的，压缩文件，里面有源程序，仿真文件等（就是所建的工程）-Digital electronic clock vhdl write, to set the alarm clock, designated chime tune, written using Quartus II 7.2 (32-Bit), compressed files, source code and simulation
clock
- there's a clock divider for DE2 altra board clock (50MHz)
clock
- 数字钟可以实现整点响铃，预置数，十二小时24小时切换(Digital clock can achieve the whole point of the bell)
world-clock
- 世界时钟，用vhdl语言编辑的一个世界时钟，基本入门编程(World clock, using a VHDL language editor of a world clock, basic entry programming)