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simulating a convolutional encoder
allows the user to input a source code to be encoded and also input the values of the generator polynomials. It outputs the encoded data bits, where 1/n is the code rate
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卷积编码器和viterbi译码器的设计与仿真-Convolutional encoder and viterbi decoder design and simulation
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FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation-Convolutional code encoder and Viterbi decoder design
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编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
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生成网格内存码率的1 / n卷积编码器的数据，在非系统的情况下，模拟二进制卷积码的编码和解码程序-Generate trellis data of a memory-m rate-1/n convolutional encoder: Nonsystematic case ，simulating encoding and decoding procedures of binary convolutional codes
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convolutional encoder
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The source code simulating the encoder and decoder of a rate 1/2 systematic convolutional code using the Maximum Likelihood Viterbi algorithm.
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convolutional encoder program
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this is a code for the convolutional encoder
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