tms320c6455 High-Performance Fixed-Point DSP TMS320C64x+™ DSP Core Enhanced VCP2 Enhanced Turbo Decoder Coprocessor (TCP2) 64-Bit External Memory Interface (EMIFA) Four 1x Serial RapidIO® Links (or One 4x), DDR2 Memory Controll

DDR2的控制器设计，完成功能的验证，以及仿真测试，(DDR2 controller design, complete function verification, and simulation test,)

本人用verilog编写的DDR2控制器，经测试可用。(I am prepared to use verilog DDR2 controller, the test is available.)