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2_to_4_decoder
- a 2_to_4 decoder example in verilog.
RS(204.188)design
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po
adpcm-and-ppt
- 包括adpcm的简单讲义 adpcm解码Verilog代码 adpcm编码代码-Including handouts adpcm decoder adpcm simple Verilog code for adpcm coding code
ptos
- 16位并行转串行译码器Verilog，以及synopsis综合结果，行为级、门级网单，均已通过仿真验证-16bit parallel to serial decoder and aynthesis result
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
H6502
- H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块和著名的6502的软件源码-The standard H.264 decoder all verilog source code, including the frame, frame, transform coding, entropy coding, filtering all modules and the famous 6502' s software source code
binary_to_BCD
- 将二进制码转换成BCD码，在verilog环境下可以封装为译码器-BCD code into the binary code in verilog environment is encapsulated as decoder
rs_encoder_decoder
- RS编解码源程序，有详细的VERILOG程序，用于纠错-RS encoder and decoder
code_83
- 3-8译码器的verilog程序实现-3-8 decoder verilog program ..............
3_8yimaqi
- FPGA verilog 3-8 译码器-FPGA verilog 3-8 decoder
decoder_3to8
- decoder 3 to 8 verilog program
decoder_5to32
- verilog 5 to 32 decoder
RS_dec
- rs（204,188）译码器，verilog实现，乘法器采用比特异或方式实现-rs (204,188) decoder, verilog achieve multiplier used than specific or way
des.tar
- DES Encoder and Decoder Verilog RTL Code
Decoder_3X8
- Verilog code for 3X8 Decoder
Desktop
- verilog 实现的可逆计数器及4-7译码器，实现并行置数，加减计数功能 -verilog achieve reversible counter and 4-7 decoder, set the number of parallelism, subtraction counting function
VITERBI_DECODER
- Verilog语言描述的应用于TD-SCDMA中的viterbi译码器rate_1-2_Viterbi_decoder-Applied in TD-SCDMA Verilog language descr iption of the viterbi decoder rate_1-2_Viterbi_decoder
rs_decoder_31_19_6.tar
- RS Decoder RTL verilog Code
anc dec
- encoder,decoder,testbench and run files