基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to

实现FPGA的MJPEG实时压缩，纯VERILOG代码实现，可以直接在FPGA内进行编译布局！(MJPEG real-time compression of FPGA implementation.Pure VERILOG code implementation, you can directly compile and layout in FPGA!)

实现jpeg图像压缩，基于FPGA的JPEG图像压缩算法实现 基于FPGA的JPEG图像压缩系统的实现(Image compression of JPEG based on MATLAB， 实现jpeg图像压缩，基于FPGA的JPEG图像压缩算法实现 基于FPGA的JPEG图像压缩系统的实现 JPEG image compression, JPEG image compression algorithm based on FPGA implementation of FPGA based J