搜索资源列表
sdModel
- sd verilog simulation model
lpddr_verilog_model
- 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
MICRON_2048Mb_ddr2
- micron ddr2 sdram verilog model and documents
digitalclock_demo
- 该程序适用于xilinx公司的FPGA开发板，spartan3E系列250型号 通过verilog编程实现数字钟的功能，下板子验证可用！-This procedure applies to xilinx FPGA development board Series 250 Model spartan3E digital clock verilog programming under the board to verify available!
DDR3-SDRAM-Verilog-Model(1)
- contains the information and codes of DDR3 memory model
uart
- uart设计的verilog代码，支持双工的串行传输，兼容synopsis 的DW_uart的编程模型-verilog code uart design, support duplex serial transmission, compatible synopsis of the programming model DW_uart
Assignment(VLSI)
- Verilog model codes for beginners
GD25LQ40_verilog
- SPI接口的flash仿真模型，用于soc仿真，本人使用过了，很好用的-spi flash verilog model
SPI_slave_mode_verilog
- spi verilog simulatin model with master -spi verilog simulatin model with master
SPI-flash
- ST公司的M25Pxx SPI flash memory的verilog仿真模型，该模型准确地描述了SPI flash memory的行为，包括读，写，擦除等操作，可以用来挂在带有SPI接口的soc外部，方便验证SPI接口。 -ST' s verilog simulation model M25Pxx SPI flash memory, the model accurately describes the SPI flash memory behavior, including readi
diff_cmp-2
- 比较器的理想模型 用Verilog-a写的-ideal model of comparator in Verilog-a
uvm_axi-master
- axi uvm vip, verification model -axi system verilog
uart
- 该源码包是uart串口协议的verilog语言模型，主要包括了3个部分：波特率产生模块，uart接收模块，uart发送模块。(The source package is UART serial protocol Verilog language model, including 3 main parts: baud rate generation module, UART receiver module, UART transmission module.)
93xx66x Verilog Model
- verilog model for 93xx6xx
24xx04 Verilog Model
- verilog model for 24xx04
eeprom
- 亲自编写并测试通过的 E2PROM 的Verilog代码，由于仅是研究学习之用，功能可以自己添加，继续完善。(The Verilog code of E2PROM is written and tested by itself. As a result of research and learning, functions can be added and perfected.)
1
- 针对矿浆管道工况调整给泄漏检测带来的干扰，准确提取泄漏信号的特征量是降低泄漏误报、漏报的关键。为此，提出了一种基于经验模态分解（EMD）、Hilbert能量谱与变量预测模型（VPMCD）相结合的泄漏检测方法。该方法首先将压力信号分解成若干个固有模态函数（IMF）之和，然后将IMF分量进行Hilbert变换得到局部Hilbert能量谱，依据能量分布的标准差选择最能准确反映矿浆管道运行工况的局部能量谱作为特征值向量，最后通过VPMCD分类器建立泄漏识别模型。将该方法应用于泄漏检测中，实验结果表明，矿
At24c02
- i2c 的verilog 仿真模型，可用于搭建仿真平台。(The Verilog simulation model of I2C can be used to build simulation platform.)