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mips_project
- 我用verilog写的risc指令集的mips的cpu。可以支持定点运算。顶层单元是top。-I used to write verilog mips risc instruction set of the cpu. To support fixed-point arithmetic. Top-level unit is the top.
cputest.rar
- 自己刚写的一个RISC的cpu，位宽16，主要是测试其中的逻辑，数据宽度是一位，可以很容易扩展,Writing just one of their own RISC the cpu, bit 16, are testing one of the main logic, data width, a, can be easily extended
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
risc
- 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
Jh_cpu
- Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
risc_cpu
- SystemC实现的一个精简指令CPU模型-risc CPU model in systemc
TCAM_2
- 经典RISC CPU 设计，和PCI8位指令单片机兼容，值得初学者看一下-Classic RISC CPU design, and PCI8 bit microcontroller compatible instruction, it is worth a look for beginners
DLX_verilog
- DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
RiscCpuA
- systemC模仿RISC CPU的简单功能-system C foumulate the simple function of RISC CPU
MTP4
- 高性能RISC CPU： • 仅需学习35条指令： - 除跳转指令外，所有指令均为单周期指令 • 工作速度: - 振荡器/ 时钟输入为DC-20 MHz - 指令周期为DC -High-Performance RISC CPU: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Sp
riscCPU
- 实现 八位RISC cpu 含有V文件和 testbents测试文件(Realization of eight bits RISC cpu)
Insiders_Guide_XC166
- The C166S V2 CPU core used in the XC166 seriesmakes extensive use of Reduced Instruction Set Computer (RISC) concepts to achieve its blend of very highperformance at modest cost.
cpusim
- C++模拟实现单线程CPU运行RISC-V指令集(C++ Simulated Implementation of RISC-V Instruction Set in Single Thread CPU)