搜索资源列表
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
PicoBlaze_Embedded_Template
- 基于xilinx的FPGA_partan3软核picoblaze的verilog程序，在picoblaze上pbus总线上挂有7段数码管，VGA，按键的驱动。-The xilinx the soft FPGA_partan3 nuclear picoblaze of verilog program in picoblaze pbus bus hang 7-segment digital tube, VGA button driven.
Verilog
- 用Verilog语言编写的多功能数字钟，用七段显示时钟-Verilog language, multi-function digital clock clock, seven-segment display
Timer
- 用verilog语言实现的定时器。在DE2-70开发板上设计，七段数码管分别用于显示时/分/秒，并带有预置时间功能。-Timer verilog language. DE2-70 development board design, seven-segment digital tubes were used to display hours/minutes/seconds, with the function of the preset time.
elevator
- 用Verilog代码进行电路设计，并在指定可编程FGPA芯片上实现电梯控制器的功能，要能够对多个楼层的请求作出判断。用七段显示器显示当前楼层，led灯表示当前电梯是上还是下状态。-Performed using Verilog code circuit design and realization of the function is specified on the elevator controller chip programmable FGPA, to be able to make a
NandBuffer
- verilog编写，含三路正弦信号发生器，三路数据乒乓缓存模块。乒乓缓存读写控制采用三段式状态机实现。-The project contains a 3-channel sine generator and a 3-channel ping-pong buffer which is written in verilog. The write and read control of buffer is implemented in 3-segment FSM.
SEG7_LUT
- altera 7-segment verilog code.