搜索资源列表
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
alu
- ALU modeling verilog codes and testbench
adder_4
- 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
inout_test
- verilog inout端口的测试程序 帮助理解Verilog语言inout端口的使用（包括Verilog程序和testbench）-verilog inout port test program to help understand the use of the Verilog language inout port
VMMing-a-SV
- vmm不错的学习资料，如何搭建testbench，很多实用的例子。推荐初学者。-study vmm of system-verilog
mux_4_to_1
- 基于verilog的四选一的设计，附带testbench，并且测试通过-Based on the four design in verilog, incidental testbench, and the test passes
pcm
- verilog 的代码，是pcm采编器，经过验证的，可以用，并且附带上testbench文件。-The verilog code pcm editorial, proven, you can use, and comes on the testbench file.
filter
- verilog implementation of structural FIR filter. Contains testbench, including sample data and coefficients.
Verilog1
- 实现了cic分频功能，分频系数D可变2~32，代码用verilog编写，其中输入数据写入主程序中，便于后人testbench的编写-Cic divide divider coefficient D variable from 2 to 32, the code is written in verilog input data is written to the main program, to facilitate future generations testbench preparation
Fsm
- 基于verilog的FSM设计，设计“101001”的序列检测器；包括testbench文件-The FSM based verilog design, design " 101001" sequence detector including testbench files
dff-n-d-latch
- Dlatch and D Flipflp code with testbench in Verilog
shift-register-and-testbench
- Shift register and testbench in verilog
adder
- 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral descr iption, ripple carry, the square root of the ca
fifo_verilog
- 16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
Haffman-encoding
- verilog implementation of huffman encoder with testbench
pud_ben
- Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)
class09_A
- Verilog 状态机编写按键消抖，并且testbench-Verilog write key debounce
testbench.sv
- RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；--RS Coding and Decoding Verilog code， implement RS（544,514)
anc dec
- encoder,decoder,testbench and run files
electrical lock
- 一个用Verilog写的电子锁工程，带testbench。(An electronic lock project written in Verilog with testbench.)