Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.

基于Verilog HDL 1、div为分频模块,晶振50M,目的是得到1HZ 2、cnt为异步清零，同步加载，同步使能的十二进制计数器。-4-Bit Binary Up Counter with Asynchronous Clear, Synchronous Load, and Asynchronous En.

verilog 写的一个增减计数器的例子，可用于位同步时钟提取中，已经经过验证，可直接添加到自己的工程中。-Verilog write an increase or decrease the counter example, can be used to extract a synchronous clock, has been validated and can be directly added to your project.