搜索资源列表
sdr_sdram_control
- 一个SDRAM控制器，verilog语言设计，并在ISE上仿真实现。（内部包含多个verilog程序）-sdram-controller,use verilog langguage,it s run sucessfull
YUV2RGB
- 关于YUV转RGB的verilog源代码、说明文档和modelsin仿真，相信对大家一定有很大的帮助，我费了好长时间才找到的！-YUV to RGB on the verilog source code, documentation and modelsin simulation, we believe that there will be a great help, I spent a good long time to find it!
iir_par_code
- IIR code. IEEE STD 1364-1995 Verilog file: iir_par.v.
color_space_converters
- Color space converter in Verilog HDL
fifo
- a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
RS(204.188)design
- RS(204,188)译码器说明 原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_po
cam_verilog.v.tar
- verilog source code for cam functionality
uart.v.tar
- uart Universal asyncronous receiver and transmitter verilog code
lfsr.v.tar
- linear feedback shift register for generator in verilog code for random sequence generation.
fibonacci_gen.v.tar
- fibonnaci generator in verilog code
seqdetector1001.v.tar
- 1001 sequence detector in verilog code for mealy state machine
synopsys_VCS_TOOL_flow
- this pdf file will gives the details of synopsys tool design space and verilog HDL ASIC design based tips.also this pdf is a power point presentation with functional verification tool of synopsys VCS tool.... VERY USEFULL FOR PROFESSORS
verilog
- verilog hdl 交通灯控制实验 源代码为y4.v-verilog hdl traffic light control experiment source code y4.v
alu.v
- a well written and yet small verilog hardware descr iption language or popularly known as simply Verilog program for an Arithmetic and Logic Unit or as popularly called ALU
mac.v
- very useful fullader for verilog
vspi.v
- 实现SPI接口功能, 语言是verilog
bin2bcd.v
- FPGA Verilog BIN 2 BCD Conversion code.
pmi_ram_dq
- pmi_ram_dq.v verilog file
pmi_dsp_casmultaddsub
- pmi_dsp_casmultaddsub.v verilog file ff
new.v
- 状态机写的axi slave，模式较少，基本功能齐全，轻便,仿真综合通过(AXI4 slave programmed by state machine approach)