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I2Cdesign.rar
- I2C总线Verilog源代码描述，ModelSim仿真,I2C bus Verilog source code descr iption, ModelSim Simulation
FFT288
- 本部分是128点的fft,经过了modelsim的仿真验证.里面采用了华莱士树等结构,整体结构采用2-It is 128 point fft,which has been verificated in the modelsim.In the verilog code ,we use hulaishi tree.we use 288 architecture to complete it.
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
Examples
- 几个简单的verilog代码，推荐用modelsim工具学习-A few simple Verilog code, recommended by ModelSim tools to learn
CPU
- verilog 实现的CPU，用Modelsim SE 6.2b 创建的工程，包含测试文件。- CPU of verilog implementation
dpll
- 本文介绍了锁相环路的基本原理，并着重分析了数字锁相环的结构、原理。利用Verilog语言对数字锁相环的主要模块进行了设计，并用Modelsim软件进行仿真。最后给出了整个系统的仿真结果，验证设计的正确性，并在现场可编程门阵列FPGA上予以实现-dpll
4-ahead_Adder
- 用Verilog HDL语言实现超前进位加法器的逻辑功能,通过ModelSim软件对4位超前进位加法器设计的仿真.-With the Verilog HDL language-ahead adder logic functions, by ModelSim software 4-ahead adder design simulation.
dcfifo_sim_modelsim_ae_gui
- dcfifo verilog source code and modelsim simulator.
code
- 是用verilog写的带uart的简单controller，使用的是mips指令，用modelsim仿真，波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
da_fir
- 基于FPGA分布式算法FIR滤波器verilog代码 （本人 小论文 代码，通过验证） 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。 为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(F
compare
- 三个数的比较，输出最大值，Verilog实现，已经建立modelsim工程，可以直接观看波形， Verilog 最大值，fpga-Verilog max value
LineBuffer
- Verilog HDL的移位寄存器的modelsim仿真
Low-Error-and-Hardware-Efficient-Fixed-Width-Mult
- VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and m
trunk
- AES128加密解密verilog程序，通过modelsim验证过-AES128 encryption and decryption verilog program, verified by modelsim
pud_ben
- Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)
test_uart
- verilog 编写的串口发送和接收模块，能够设定停止位和校验位，并且包含了modelsim仿真文件。-verilog prepared by the serial port to send and receive module, capable of setting the stop bit and the parity bit, and includes modelsim simulation files.
cpu_me
- 采用verilog编写的cpu,modelsim仿真均实现8条指令功能，有虚拟ram和rom-Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom
parallel-to-serial
- 用Verilog语言编程实现并行转串行，并在modelsim中仿真出波形。-programming to realize parallel to serial using Verilog language , and simulating waveform in the modelsim.
serial-to-parallel
- 用Verilog语言编程实现串行转并行，并在modelsim中仿真出波形。-programming to realize serial to parallel using Verilog language , and simulating waveform in the modelsim 。
SD SPI模式verilog外加modelsim仿真结果
- SD卡的SPI模式verilog代码，外加modelsim仿真结果。(SD card's SPI mode Verilog code, plus the simulation results of modelsim.)