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singlecycle_mips
- single cycle mips design by verilog.
single-clock-CPU
- 单时钟周期CPU，verilog语言编写，quartusII运行-A single clock cycle CPU
lab07
- 利用verilog语言编写一个单周期cpu实现加减乘除等十六条基本指令，模拟仿真通过。-Use verilog language to achieve a single cycle of addition, subtraction, etc. cpu sixteen basic instructions, simulation pass.
sc_computer_2
- Verilog单周期CPU实现,可以实现简单的mips指令，附Verilog源码-Verilog achieve single-cycle CPU