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stackfiles
- VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower la
635355963606373750
- 本文介绍了应用FPGA实现对高速A/D转换芯片的控制电路，介绍了这一控制的设计思想，并提出了通过双口RAM实现FPGA与慢速度的单片机进行双机数据通信处理的解决方案。- Data acquisition is an item of indispensable technology which is essential to the industrial control system. As the increasing need for speed performance of the da
pc_fpga_com_latest.tar
- Example Project on how to communicate PC to FPGA using UDP/TCP packets-Example Project on how to communicate PC to FPGA using UDP/TCP packets
socket_apps
- FPGA与pc socket模式下通信 所用的板子为ml605_AxiEth_8Kb_Cache-FPGA and socket PC mode of communication used by the board for the ml605_AxiEth_8Kb_Cache
raw_apps
- FPGA与pc raw模式下通信 所用的板子为ml605_AxiEth_8Kb_Cache-FPGA and raw PC mode of communication used by the board for the ml605_AxiEth_8Kb_Cache
socket_apps
- FPGA与pc socket模式下通信 所用的板子为sp605_AxiEth_8kb_Cache-FPGA and socket PC mode of communication used by the board for the sp605_AxiEth_8kb_Cache
raw_apps
- FPGA与pc raw模式下通信 所用的板子为sp605_AxiEth_8kb_Cache-FPGA and raw PC mode of communication used by the board for the sp605_AxiEth_8kb_Cache
raw_apps
- FPGA与pc socket模式下通信 所用的板子为AC701_AxiEth_100MHZ_32kb-FPGA and socket PC mode of communication used by the board for the AC701_AxiEth_100MHZ_32kb
socket_apps
- FPGA与pc socket模式下通信 所用的板子为AC701_AxiEth_100MHZ_32kb-FPGA and socket PC mode of communication used by the board for the AC701_AxiEth_100MHZ_32kb