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JTD
- 带左拐的交通灯设计与25进制的加法计数器,Maxplus2软件中的Verilog语言编写-Neunggok with the design of traffic lights at 229 with the addition of 25 counters, simulated software Verilog language
mul_fft_96bit
- 基于Fermat数变换的大数相乘运算的Verilog实现,可应用于RSA加法芯片中。-Fermat number transform based on multiplying large numbers operations Verilog implementation, can be applied to RSA chip.