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Xinlinx_Spartan3E500_RevD_10.1
- 这个是我使用xilinx EDK 10.1建立的用语移植petalogic的uclinux发行版本petalinux-v0.4-rc2的Platform工程，开发板使用的是Spartan3E Starter Kit。在这个基础上可以直接裁剪内核后在FPGA中运行uclinux。内核源码可以到developer.petalogix.com下载。,This is a xilinx EDK 10.1, I use the term established by the uclinux transpla
FPGA
- 这是一个基于FPGA的加密/解密算法的简单介绍，并阐述了它的好处。-This is an FPGA-based encryption/decryption algorithm is a brief introduction and explained its benefits.
khalil2006_true_random_number_generator
- a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are requ
fpga_uclinux
- 关于UCLINUX和FPGA的应用研究，很好的简介！-FPGA on the UCLINUX and applied research, a very good profile!
fsk
- 关于FSK调制的FPGA实现，有VHDL源码-FSK modulation on the FPGA, a VHDL source code
lcdc.tar
- Program to control an LCD connected to a Xilinx xc3030 FPGA from Linux
FPGA-Xilinx
- 上载一篇：FPGA设计高级技巧Xilinx篇，希望对大家有点用。-Upload a: FPGA design tips for Xilinx articles, we hope to some use.
AES-implementation-based-on-FPGA
- 一种基于FPGA的AES加解密算法设计与实现，对于对AES算法效率的研究有参考作用-FPGA-based AES encryption and decryption algorithm design and implementation of the AES algorithm for the efficiency of a reference
sms4
- SMS4是用于WLAN的国内官方公布的第一个商用密码算法，具有较好的抗破解能力。本代码提出了一种新型的基于FPGA硬件实现的SMS4分组密码算法电路的设计。-SMS4 for WLAN in the domestic first official commercial cryptographic algorithms, and has good resistance to cracking ability. The code proposes a new FPGA-based hardware
Linux-driver-development2
- 作者：华清远见嵌入式学院。《Linux设备驱动开发详解》（08&09年度畅销榜TOP50）第2章、驱动设计的硬件基础。本章讲解底层驱动工程师必备的硬件基础，给出了嵌入式系统硬件原理及分析方法的全景视图。2.1节讲解微控制器、微处理器、数字信号处理器以及应用于特定领域的处理器各自的特点。2.2节对嵌入式系统中所使用的各类存储器与CPU的接口、应用领域及特点进行了详细讲解。2.3节讲解常见的外设接口与总线的工作方式，包括串口、I2C、USB、以太网接口、ISA、PCI和cPCI等。嵌入式系统硬件电路
project-report
- documentation of Implementing a 1024-bit RSA on FPGA
aes-encryption
- 为实现AES加密设计的高速实现，本设计引进了一种AES的并行设计算法，整体结构和加密进程，基于FPGA本身的特征和算法，设计使用并行处理算法来实现并行处理进程。-To implement the design of the AES algorithm with a high speed, the thesis introduce the principia mathematica of AES algorithm, integral structure and the Encryption pr
paixu
- TD-SCDMA的长期演进TD-LTE。为减轻TD-LTE综测仪开发中调试的复杂性，通过研究分析TD-LTE系统原语，提出了一种基于DSP TMS320C6455和FPGA 5vsx95tff1136(Xilinx)芯片的原语追踪平台。-Long-term evolution of TD-SCDMA, TD-LTE. TD-LTE system primitives through research and analysis in order to reduce the complexity o
AES-based-on-FPGA-jiami
- 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
Encryption-SATA-IP-Based-on-FPGA
- 本文首先分析了目前常用的硬盘数据加密方法，并在比较各种加密方案的基础上给出了基于FPGA的加解密SATA IP设计方案。本文介绍设计SATA IP相关的基础知识，包括SATA的体系结构。本sata IP已在Xilinx spartan-6系列上实现并产品化，具有低成本优势，且可以根据用户意愿更换加密算法和使用私有的加密算法。本文还论述了加密SATA IP的各种应用前景。-This paper firstly analyzes several common ways of Hard Disk da
VHDLsonic
- FPGA把每路测距单元计算得到的障碍物距离信息通过RS-232接口传输到上位机，便于后续应用或上位机界面显示。同时，为了提高测距仪器的便携性，还为其安装了液晶显示屏，实时显示各路距离信息-FPGA put obstacles ranging from Each unit calculates the information obtained via RS-232 interface to transfer to the host computer to facilitate subsequent
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
AES-pipelined-architecture
- AES算法，采用FPGA实现，重点描述了流水线设计，使用才方法使加解密具有很高的吞吐率-An AES crypto chip using a high-speed parallel pipelined architecture
ec_bhf
- This a driver for EtherCAT master module present on CCAT FPGA. Those can be found on Bechhoff CX50xx industrial PCs. -This is a driver for EtherCAT master module present on CCAT FPGA. Those can be found on Bechhoff CX50xx industrial PCs.
FPGA
- 扫频功能key2level.v 按键点击一次，输出信号电平变化一次； key2pulse.v 按键点击一次，输出信号产生一个周期的脉冲信号；-weep function key2level.v Press the button once, the output signal level changes once Key2pulse.v Press the button once, the output signal to generate a cycle o