搜索资源列表
aes_core
- AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use,
desimplementation
- 一个关于DES算法的verilog语言实现,包括了各个实现模块以及测试模块-a DES algorithm on the Verilog language, including the realization of the various modules and test modules
JTD
- 带左拐的交通灯设计与25进制的加法计数器，Maxplus2软件中的Verilog语言编写-Neunggok with the design of traffic lights at 229 with the addition of 25 counters, simulated software Verilog language
des
- 用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过
CCD_Verilog_1014
- 基于CPLD器件的线型CCD东芝TCD1501的驱动程序，用verilog语言开发。
aes-verilog-imp
- AES加密算法的硬件实现，硬件语言为verilog-AES encryption algorithm hardware implementation, hardware verilog language
madplay-0.16.1b
- 经典的C语言MP3编码解码实现,可以在linux/unix平台下编译运行. -Classic C language realize MP3 codec, you can linux/unix platform running under the compiler.
AES_verilog
- AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
daima
- 数字电路Verilog语言代码 例如编码器，触发器，计数器等-Digital circuits Verilog language code such as encoders, flip-flops, counters, etc.
SDRAM_verilog-serial-port
- FPGA对sdramd的操作，verilog语言设计！-FPGA SDRAM verilog
d10-counter
- 十位加法器，用verilog语言编写，适用于verilog学习。-10-bit adder, using Verilog language, applicable in verilog learning.
clk-10divide
- 十分频，用verilog语言编写的程序，使用与verilog学习。-The very frequency, the Verilog language program, the use of learning verilog.
ucliunx
- 采用verilog语言，在fpga上实现uclinux的移植，使用nios 2 ，成功完成移植-Verilog language uclinux porting nios fpga on the successful completion of the transplant
comp
- 四位比较器，用verilog语言编写，在modelsim软件中编译仿真成功，可以下载-Four comparators, using verilog language, compiled simulation in modelsim software successfully, you can download to see
final-project-dpim
- FPGA模块设计，包括脉冲发送，信号处理，以及接收，系统是基于windows系统，verilog语言实现。-FPGA module design, including pulse transmission, signal processing, and receive, the system is based on the windows system, verilog language。
final-project-dppm
- FPGA模块设计，包括脉冲发送，信号处理，以及接收，系统是基于windows系统，verilog语言实现-FPGA module design, including pulse transmission, signal processing, and receive, the system is based on the windows system, verilog language
multiplication-module
- Verilog语言通过并行相加的方式实现乘法模块-Verilog language multiplication module by adding a parallel way.
trunk
- 用Verilog语言仿真3种NoC中路由器的实现流程，验证其性能。-Simulation of 3 kinds of NoC routers in the implementation process of the Verilog, verify its performance.
src
- 用于国密4的加解密算法实现，采用verilog 语言，可进行vivado仿真，vivado版本是2013，结果经测试正常，适合从事相关行业的工作人员进行借鉴和开发。(The code is realized and simulated by verilog. The simulation result has been confirmed by the author. It is recommended to download by the researchers who are in the
Divider
- 用Verilog HDL语言实现分频器，初学，简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)