伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.

NetFPGA开发基础包，里面有相关的实例工程，也有相关的源码，verilog HDL，C，JAVA等-NetFPGA development base package, there are examples of related works, there are also relevant source, verilog HDL, C, JAVA, etc.