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aes_encryption
- aes加密算法的VHDL代码实现，在FPGA芯片上调试过
Algorithms
- 密码算法AES,DES,IDEA,MD5等的基本理论和硬件加速方案，对算法进行fpga硬件加速的优点等
aes加密算法实现，经过FPGA验证的
- aes加密算法实现，经过FPGA验证的！,aes encryption algorithm, after FPGA validation!
RIJNDAEL_DE_TOP
- AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
khalil2006_true_random_number_generator
- a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are requ
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
systemcaes_latest.tar
- 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
AES-implementation-based-on-FPGA
- 一种基于FPGA的AES加解密算法设计与实现，对于对AES算法效率的研究有参考作用-FPGA-based AES encryption and decryption algorithm design and implementation of the AES algorithm for the efficiency of a reference
AESFPGA
- 论文介绍了AES算法在FPGA上的实现功能，对AES算法过程进行了优化。-This paper introduces the AES algorithm in FPGA implementation function of the AES algorithm to optimize the process.
aes-encryption
- 为实现AES加密设计的高速实现，本设计引进了一种AES的并行设计算法，整体结构和加密进程，基于FPGA本身的特征和算法，设计使用并行处理算法来实现并行处理进程。-To implement the design of the AES algorithm with a high speed, the thesis introduce the principia mathematica of AES algorithm, integral structure and the Encryption pr
des1
- 基于ＦＰＧＡ的ＡＥＳ加密算法的实现 由于其较高的保密级别，AES算法被用来替代DES和3一DES，以适应更为严苛的数据加密需要。-FPGA Implementation of Real-Time Adaptive Image Thresholding
AES-based-on-FPGA-jiami
- 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
AES_128
- AES 128 bit with various device interface on FPGA
Project
- 基于FPGA的AES算法的VHDL实现，低内存模式-aes vhdl code
FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR
- Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation
AES-on-FPGA
- AES算法在FPGA上的实现，对AES算法所用的器件资源进行了总结-AES on FPGA the Fastest to the Smallest
AES-pipelined-architecture
- AES算法，采用FPGA实现，重点描述了流水线设计，使用才方法使加解密具有很高的吞吐率-An AES crypto chip using a high-speed parallel pipelined architecture
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl
GCM-AES_Implementation_Spec_v2
- AES GCM 算法介绍，对AES算法实现有一定帮助。-This document aims to explore hardware implementation of GCM-AES mode of operation specifically targeting FPGA [1] (Field Programmable Gate Arrays). The aim of such an implementation is to benchmark GCM-AES on FPGA in term