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bianmaqi
- 一个完整的viterbi(2,1,7)编码程序，使用的是Verilog语言
decode.rar
- LDPC的Verilog程序源代码，包括仿真数据等。文件很大，请慢慢下载,LDPC of Verilog source code, including the simulation data. Large file, please download slowly
turbo_encoder.rar
- turbo码_verilog_编码源文件,turbo code _verilog_ coding source files
ldpc_vc
- ldpc编码的vc例程，编译通过，详细的解释了ldpc编码的原理-vc-encoded ldpc routine, the compiler through a detailed explanation of the principle of encoding ldpc
verilog
- 介绍了一种SPI从机的接口verilog编码-verilog code for spi slave
PCMverilog
- 实现了数字通信系统中PCM编码，用Verilog硬件描述语言编程在FPGA上实现的。-Achieved in the PCM coded digital communication system, using Verilog hardware descr iption language programming implemented on the FPGA.
ldpcverilog
- verilog编写的ldpc编码的源代码 -ldpc prepared verilog source code
fangzhen
- 卷积码和循环码的verilog编码以及仿真结果图，-Convolutional codes and cyclic codes and the coding verilog simulation results map
RS_5_3_CODEC
- 完成RS（5，3）编码程序，运用Verilog语言。-Complete the RS (5,3) coding process, the use of Verilog language.
tcm_enc
- 用Verilog实现（2,1,2）卷积码和8—PSk调制相结合的TCM编码器-Using Verilog realize (2,1,2) convolutional code and 8-PSk modulation encoder combination of TCM
bch_enc
- bch编码模块，verilog程序，串行输入，串行输出-The BCH encoding module, Verilog program, serial input, serial output
RS_codeVerilog_program
- 运用verilog，实现了RS（255,247）的编码和BM算法的迭代译码，已通过仿真验证。-Using verilog, the RS (255,247) coding and the iterative decoding of the BM algorithm are implemented and verified by simulation.
rs_200_168
- Verilog实现的DVB（200,168）的RS编解码程序，xilinx 平台，经过验证(Verilog implementation of DVB (200168) RS codec program, Xilinx platform, verified)
8b10b Verilog
- 采用verilog语言基于查找表描述8b10b编码源代码(Using Verilog language to describe 8B10B encoding source code based on look-up table)
8398489
- 一个完整的viterbi(2,1,7)编码程序,使用的是Verilog语言()
rs_15_11
- ReedSolomon RS(15,11) Verilog 编码和解码测试程序 编码有两种实现方式 串行和并行方式(ReedSolomon RS(15,11) Verilog Encoder&Decoder)
eyye
- 一个完整的viterbi(2,1,7)编码程序,使用的是Verilog语言()