搜索资源列表
c6_PLLsim
- 这个程序是matlab用来来对锁相环（PLL）进行仿真的，这样的选择基于多方面的考虑-This procedure is used Matlab to the phase-locked loop (PLL) simulation, This choice is based on a number of considerations
PhaseLockedLoop
- ％The phase locked loop(PLL),adjusts the phase of a local oscillator ％w.r.t the incoming modulated signal.In this way,the phase of the ％incoming signal is locked and the signal is demodulated.This scheme ％is used in PM and FM as well. ％We wi
verilog
- 采用用verilog语言编写的全数字锁相环的源代码。-Verilog language used by all-digital phase-locked loop' s source code.
Cayiwei
- GPS的matlab程序，用于对产生的ca码进行移位，用在锁相环跟踪中对ca码调增 -GPS-matlab program code used to generate the ca shifting, with the phase-locked loop tracking code on the ca be adjusted by
pll
- 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
Pllrrrr
- 锁相环（非科斯塔斯环） 对波动频率进行锁定，并且对信号进行解调。画图7个显示过程及参数-The phase locked loop(PLL),adjusts the phase of a local oscillator.the phase of the incoming signal is locked and the signal is demodulated show the process and references in 7 figures
PLL
- 锁相环问题的仿真，可以解决数字锁相环的仿真问题-Phase-locked loop simulation problem, can solve the problem of digital phase-locked loop simulation
slla120
- 锁相环是一种反馈电路，其作用是使得电路上的时钟和某一外部时钟的相位同步。PLL通过比较外部信号的相位和由压控晶振（VCXO）的相位来实现同步的，在比较的过程中，锁相环电路会不断根据外部信号的相位来调整本地晶振的时钟相位，直到两个信号的相位同步。-PLL is a feedback circuit, and its role is to make the clock circuit and a phase of external clock synchronization. PLL signal
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
dpll
- All Digital Phase-Locked Loop verilog source code
PrenticeHallPrincipleofCommunicationSystemSmulatio
- 本书分成三部分，第一部分讨论了仿真的作用和方法论。第二部分介绍了采样定理，滤波器模型、锁相环等的仿真。第三部分是高层建模与仿真方法。-The book is divided into three parts, the first section discusses the role of simulation and methodology. The second part of the sampling theorem, the filter model, phase-locked loop
gsmyf9024
- Atmel Mega16单片控制LMX2326实现锁相环-Atmel Mega16 chip phase-locked loop control to achieve LMX2326
Phasell
- 基于matlab的锁相环的仿真，注释详尽-Phase-locked loop based on matlab simulation, comments in detail
Pll
- 锁相环解调调制信号，效果很好，这是电路pcb板-Phase-locked loop demodulation modulation signals with good results, this is the circuit board pcb
weitongbu
- 数字锁相环实现位同步信号的提取,含电路图，和源代码-Digital phase-locked loop to achieve bit synchronization signal extraction, including schematics, and source code
frerecov
- 通信系统中有关于利用锁相环完成载波跟踪恢复的仿真功能-Communication system using phase-locked loop on the completion of the simulation function to restore the carrier tracking
The_shortwave_high-speed_QAM_signal_fast_without_j
- 一种短波高速QAM信号快速无抖动码元同步方案的设计,文章基于Gardner定时误差检测算法、预滤波和一阶过零检测锁相环理论,结合卡尔曼 滤波算法,设计了一种快速无抖动的短波高速QAM信号全数字解调码元同步方案,从理论上 推导了方案中各个参数的设置方法,并在不同的信道环境下测试算法的性能,仿真结果显示 该方案具有优良的性能。 -A short high-speed QAM signal symbol timing quickly without jitter in the desi
shiyanbaogao
- 了解ISE平台的基本环境，编译程序，在MC8051 IP核中，要求实现：增加PLL锁相环，扩大内部RAM，定时器，串口和外部中断等资源，并增加乘法器和除法器的功能。-ISE platform to understand the basic environment, compiler, the MC8051 IP core, the requirement to achieve: increased PLL phase-locked loop, expanding the internal RAM
loop-parameters-selection
- 二阶锁相环设计中环路参数的选择。详细推导了参数设置。-Two order phase locked loop design of loop parameters selection
pll_carrier_syn
- 本程序是锁相环的仿真程序，具有接收端载波同步的功能。注释详尽，程序规范。发端的调制方式有单载波调制，BPSK调制，QPSK调制可供选择。程序中有星座图，锁相环的频差、相差图，以及解调后的基带波形。-This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications.