上传的代码是基于Xilinx下的ISE开发平台，用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.

自己用xilinx ise编写的分频器程序，可以奇分频偶分频，分频系数可以自己设置。方便产生各种时钟信号-Divider program prepared using the Xilinx ISE, odd even divide divider division factor can set up their own. And convenient produce a variety of clock signal

文件里包括了利用xilinx ISE 设计波形发生器所要用到的三角波，正弦波，矩形波rom文件-File including the use of the Xilinx ISE design waveform generator to use the triangle wave, sine wave, square wave rom file