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decoder
- 用verilog编写的bch译码器，包括测试文件，随机加载了比特流，进行了测试。-Prepared using Verilog BCH decoder, including test papers, random load the bit stream to carry out the test.
viterbi
- viterbi encoder and decoder modeling verilog
yima
- Verilog语言描述38译码器功能，适用于ISE或者quartus软件-Verilog language descr iption 38 decoder function for ISE or quartus software
BCH_dec_verilog
- BCH decoder based on Verilog design
XOR_tree
- This source code is a check node unit for LDPC decoder. The language is Verilog HDL.
rs_15_11
- ReedSolomon RS(15,11) Verilog 编码和解码测试程序 编码有两种实现方式 串行和并行方式(ReedSolomon RS(15,11) Verilog Encoder&Decoder)