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sim_PLL
- This shows how the phase lock loop can be designed and system parameter dendancy verified through simulation
Design-of-All-Digital-FM-Receiver-Circuit
- all digital phase lock loop
PLL1
- 锁相环跟踪主程序,里面有参数的详细说明,适合初学者理解锁相环的跟踪过程-simulation code for phase lock loop
任务四 Gardner位同步算法与锁相环联合仿真
- Gardner位同步算法与锁相环的联合仿真程序.加入了时偏和频偏,能很好地锁定时偏和频偏,得到最佳采样输出。(Gardner bit synchronization algorithm and phase-locked loop joint simulation program, adding time offset and frequency offset, can well lock the bias and frequency offset, get the best sampling o