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uart_VHDL
- uart的vhdl实现代码 分模块设计和状态机设计 不错的，用它没错-UART achieve the VHDL code modular design and state machine design good, the right to use it
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
pro104_uart
- uart的代码，经实际运行可以通信，是xilinx uart 代码的改进，网上的xilinx uart代码有很多bug，用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
UARTcode
- 串口UART通用异步接收/发送器的VHDL 源代码-Serial UART code
a_vhd_16550_uart_latest.tar
- 16550 uart vhdl source code
uartvhdl
- 该程序是基于UART的控制，有VHDL和verilog的源码，共有兴趣的朋友参考-The program is based on the UART' s control, there is VHDL and verilog source code, a total interest of a friend reference
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
basic_uart
- uart vhdl code with test bench working fine njoy maadi