搜索资源列表
f2
- 96位矩阵循环乘法，verilog实现，
16QAM_verilog 使用Verilog实现全数字的16QAM调制器
- 使用Verilog实现全数字的16QAM调制器，假设载波的频率为1MHz，数据比特率为100kbit/s.包括源代码和testbench-use verilog to realize 16qam,carrier frequency is 1MHz,data rate is 100kbit/s.including source code and testbench
uart
- Verilog实现串口收发数据，包括整个quartus工程-Verilog serial port to send and receive data, including the whole quartus project
cic_comb
- cic滤波器的Verilog实现 cic滤波器的Verilog实现-cic滤波器的Verilog实现
viter2
- verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
PCMverilog
- 实现了数字通信系统中PCM编码，用Verilog硬件描述语言编程在FPGA上实现的。-Achieved in the PCM coded digital communication system, using Verilog hardware descr iption language programming implemented on the FPGA.
ldpc
- 最近在做毕设，ldpc码的编解码实现，这个是verilog实现。-Recently completed the set up to do, ldpc code codec implementation, this is the Verilog implementation.
D_BLAST44
- MIMO 4*4系统D-BLAST编译码方案，利用ISE仿真环境，verilog编程实现。-MIMO 4* 4 system codec D-BLAST program, using ISE simulation environment, verilog programming implementation.
EPPsram
- 用verilog实现的epp与sram通信的程序-epp communicate with sram in verilog
uart16550
- Ｕａｒｔ 串口的verilog实现已调试通过-verilog
RS_Verilog
- RS码的FPGA实现，verilog语言形式，好参考资料-FPGA realization of RS code, verilog language form, a good reference
viterbi
- 一个vitrtbi算法的参考实现,verilog的-A reference implementation vitrtbi algorithm, verilog of
fir
- 用verilog实现fir滤波器,实现了一个8阶的fir滤波器-design the fir filter use verilog lanuage
UART
- 利用Verilog实现一个UART接口，包含三个源文件rcvr.v\txmit.v\uart.v -Verilog realization of the use of a UART interface, the source file contains three rcvr.v \ txmit.v \ uart.v
min
- verilog编写的基于并行流水线结构的16阶滤波器的实现-filter
UART
- Verilog实现的UART程序，用ISE打开工程文件即可-Verilog implementation UART program, open the project file with the ISE can be
verilog_16QAM
- 使用verilog实现全数字16QAM调制器，载波频率1MHZ，数据比特流的速率为100Kbps,-the modulation of 16QAM based on FPGA
Frame_Detection
- ofdm系统中的完整帧同步模块，基于verilog实现。-ofdm system full frame synchronization module, based on verilog implementation.
Uart-Verilog
- verilog实现串口通讯，包括verilog代码和testbench代码-verilog serial communication, including the verilog code and testbench Code
FPGA实现串口解析
- 用verilog语言不同的编写方式来 实现各种复杂串口通讯(use the verilog to uart)