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async_fifo.v
- the verilog model of async_fifo.
crc_interp_2_single
- 单级cic数字积分梳妆滤波器实现，格式.v代码，verilog语言编程-Single-stage CIC filter dressing integral digital format. V code, verilog language programming
UART
- 利用Verilog实现一个UART接口，包含三个源文件rcvr.v\txmit.v\uart.v -Verilog realization of the use of a UART interface, the source file contains three rcvr.v \ txmit.v \ uart.v
walshseq.v
- generation of walsh sequence in verilog
UART发送接收奇偶校验
- 状态机，串口收发，以及奇偶校验。 even_parity.v奇偶校验； receive_byte.v字节接收； send_byte.v字节发送(state machine,UART even_parity.v even parity; receive_byte.v receiving byte; send_byte.v sending byte)