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GetRomData
- 生成4种方式的DDS输出的读表程序的VHDL源代码程序。-four ways generation of DDS output of the meter reading procedures VHDL source code procedures.
iic_vhdl
- iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC u
dataacquisitionwithFPGA
- 用fpga+usb显现的4通道800K的数据采集方案。-Fpga+ usb with emerging 4-channel data acquisition program of 800K.
DDR_interface
- 高速DDR存储器数据接口设计实例. 1. 将文件拷入硬盘 2. 产生DQS模块 3. 产生DQ模块 4. 产生PLL模块 5. 拷贝以上步骤生成的文件到子目录【Project】中 6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块 7. 编译并查看编译结果 -High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS
RS_Verilog
- RS码的FPGA实现，verilog语言形式，好参考资料-FPGA realization of RS code, verilog language form, a good reference
HANMINGMA
- 7,4汉明码的编译码原理，用VHDL语言实现的，需要的请下载-Hamming code encoding and decoding of 7,4 principle, using VHDL language and the clear need to download
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
muxdemux_4E1(E2)_to_1E2(E3)
- framer Deframer core multiplexed 4 E1(E2)channel s to one E2(E3) stream at 8.448Mbps(34.368Mbps) rate .
iir_filter
- 用2个2级iir滤波实现的4阶iir滤波，采用16bit量化系数，其中14位有效位，经过与matlab的4阶iir滤波对比，输出结果完全一致。(The 4 order IIR filtering is implemented by two 2-level IIR filtering, and the 16bit quantization coefficient is adopted, in which 14 bit effective bits are compared with the 4 o