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wb_lpc_latest.tar.gz
- Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
bch9.1
- 这是我做的一个BCH译码模块硬件语言模块，这么好的东西上传上来还不让下载-This is what I do a BCH decoding hardware module language module, so good things do not let up upload download
I-rife
- 频率估计，是一种比较简单的算法，很基础，有助于初学者应用-Frequency estimation, is a relatively simple algorithm, it is based applications to help beginners
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
src
- DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output. -DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output.
ULPI
- I am uploading the source code of USB 2.0 ULPI
a1
- i included the coding for the ofdm modem in vhdl
ethernetif
- ethernet的初始化,对ethernet的驱动代码写的比较详细(It is demo code about ethernet init.,I just test it .)
VHDL实用教程_潘松_王国栋
- vhdl经典教程，本人亲自学习实践，很有用。带你进入fpga世界。(VHDL classic tutorials, I personally learn practice, very useful. Take you into the FPGA world.)