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grlib-gpl-1.0.15-b2149.tar
- free hardware ip core about sparcv8,a soc cpu in vhdl-free hardware ip core about sparcv8. a soc cpu in vhdl
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
bluetooth.tar
- 蓝牙的一个ip RTL 核，不知道对大家有没有用？谢谢。-this is an IP core of blutooth.
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
usb_funct
- usb 2.1 IP 的 东西 很好的 是 我的 -usb2.1 IP it s so eay to me to you
i2c_latest.tar_1
- I2C的OPEN CORE 的代码，很使用，可以直接改参数-I2C open core ip。verilog
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
51
- 完整的8051的IP核，用VHDL语言描述-the ip core of c8051,described in VHDL language
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband