串口数据记录波形分析仪(适于嵌入式系统设计) Ver 6.5-Serial data recording waveform analyzer (for embedded system design) Ver 6.5

基于FPGA设计，verilog语言变成的，SPI通用接口模块，顶层已封装成类似标准的FIFO接口；提供仿真文件；仿真器为modelsim10.0c，波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard