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uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
uart16750_latest.tar
- Implements a 16550/16750 UART core
i2c_latest.tar_1
- I2C的OPEN CORE 的代码，很使用，可以直接改参数-I2C open core ip。verilog
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
51
- 完整的8051的IP核，用VHDL语言描述-the ip core of c8051,described in VHDL language