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pci-verilog
- USB及PCI总线设计的一些源代码(经测试)-USB and PCI bus design some of the source code
usb1_funct
- USB2.0的IP核(详细verilog源码和文档)-USB2.0 IP core (detailed Verilog source code and documentation)
SLAVE-FIFO-16BITS
- CY7C68013a的slavefifo的固件源代码,keil编写,以及使用FPGA向EP6端点写数据的verilog源代码,没有错误,可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!