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Music
- MAX plus VHDL语言 实现音乐的演奏
CLK_DIV
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
ClockDividedBy10
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
0zzClockDividedBy10
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
hehaClockDividedBy10
- 爱用硬件描述语言VHDL实现输入时钟10分频输出-divide CLOCK by 10 using VHDL
Sinewavegenerator
- 利用VHDL语言设计的正弦波发生器，只是基本操作，仅供学习参考！-Design using VHDL language of sine wave generator, but the basic operation of reference for learning!
MUSIC
- 频率音乐发生器硬件描述语言VHDL设计程序代码-the vhdl code for muisc player
adder
- 基于vhdl硬件描述语言的8位加法器的设计-Based on the design of the 8-bit adder VHDL hardware descr iption language
h265enc_v1.0
- 用vhdl语言编写的h.265编码器，可用于xilinx或altera的fpga(h.265 encoder written by vhdl. It can be download to xilinx or altera's fpga)