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DecimationFilterDesignforDDCandImplementingItwithF
- 本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性
cic_4_dec
- 实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波
CIC_deci4.rar
- cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
CIC_DEC
- CIC抽取滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC decimation filter design, CIC filter order of 8 times 5 samples.
cic_dec_8_three
- 8位三级CIC抽取滤波器，VHDL语言版~-8 three-CIC decimation filter
CIC8_fir_comp_mlab
- CIC抽取补偿滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC compensation filter design samples, CIC filter order of 8 times 5 samples.
CIC4_fir_comp_mlab
- CIC抽取补偿滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC compensation filter design samples, CIC filter order 4 times using 5 samples.
CIC_DEC_3
- CIC抽取滤波器设计，CIC滤波器采用5阶3倍抽取。-CIC decimation filter design, CIC filter order 3 times 5 samples.
CIC_DEC_4
- CIC抽取滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC decimation filter design, CIC filter order 4 times using 5 samples.
CIC_DEC_6
- CIC抽取滤波器设计，CIC滤波器采用5阶6倍抽取。-CIC decimation filter design, CIC filter stage 6 times 5 samples.
cic_fpga
- CIC抽取滤波器的改进及其FPGA的实现.pdf-cic _fpga
cic_dec_8_five
- CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
fir_dec3
- FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
digitaldownconversionbygpga
- 研究了高倍抽取的数字下变频设计，重点分析了基于级联积分梳状滤波器和级联半带滤波器的多级抽样频率算法。-Extraction of the high-powered digital down-conversion design, the focus of a cascaded integrator comb filter based on cascaded half-band filter and the multi-level sampling frequency algorithm.
CIC
- cic滤波器，完全通过验证，32倍抽取，4阶-cic filter, fully validated, 32-fold extract, 4 bands
HBfir
- 自己编写的半波带滤波器，可应用于抽取滤波器-failed to translate
cicfilter
- 基于多速率信号处理原理,设计了用于下变频的CIC抽取滤波器,由于CIC滤波器结构只用到加法器和延迟器,没有乘法器,很适合用FPGA来实现-This article describes the design of a CIC filter based on the signal processing theory.Because of its structure only using the adder and the delay devices without multiplier,it is
CIC-filter-design
- CIC滤波器的设计，实验中用到的所有完整的工程文件在test5文件夹下。 （1）一级CIC滤波器的设计，完整的工程文件包含： cic_only.mdl ma_only_standard.mdl （2）多级CIC滤波器的设计，完整的工程文件包含： cic_5th_order_pipe1.mdl cic_5th_order_pipe2.mdl fixed_point_cic.mdl （3）CIC插值和抽取滤波器的设计，完整的工程文件包含： cic
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
DDC中的抽取滤波器设计及FPGA实现
- 本文对下变频模块中抽取滤波进行了详细的分析，并详细阐述了其FPGA的实现过程和方法(In this paper, the decimation filtering in the down conversion module is analyzed in detail, and the realization process and method of FPGA are discussed in detail)