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XPS_EMC.rar
- Xilinx EDK中SOC使用外部存储器接口（EMC）的方法，并用ISP1581举例说明了如何与时分复用总线（8051单片机总线）设备进行连接，有Verilog源代码。,Xilinx EDK in SOC using external memory interface (EMC) methods, and examples of how ISP1581 with the TDM bus (8051 bus) devices to connect, there Verilog source co
Encode
- 十六位编解码器，时分复用，很好的一个程序-Codec 16, time division multiplexing, a process well
tdm_latest[1]
- TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换-TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange
dfilter
- 用FPGA实现信道化接收机算法，共256个信道，处理时钟40M，时分复用完成算法实现-FPGA implementation using channelized receiver algorithm, a total of 256 channels, processing clock 40M, time division multiplexing algorithm to complete
a
- 多路复用信号产生电路的建模与VHDL设计 时分多路 原理 模型 模块建模-Multiplexed signal generation circuit modeling and design of time-division multiplexing principle VHDL model modeling module
CC1110_TDMA
- 利用集成的51单片机控制实现cc1110无线通信模块在传输时的时分复用功能-Integrated single-chip 51 control cc1110 wireless communication module in the transmission of time-division multiplexing function
ARM_test_fiber
- 针对FPGA接口的时分复用多路数据收发，已测试通过-Time division multiplexing data transceiver
jishu
- 计数器，数码管显示，使用时分复用和七段译码实现数码管显示，计数器则是分频实现-Counters, digital display, use time division multiplexing and seven-segment decoder for digital display, the counter is then the divider to achieve
multiplex
- 四路信息时分复用和解复用，包含串并转换，并串转换，提取帧同步，分频，移位寄存器。-Quad information time-division multiplexing and demultiplexing, contains the string conversion, parallel-serial conversion, extracting the frame synchronization, frequency division, the shift register.
bpsk
- bpsk系统，时分复用，adc转化，dac转化。-the bpsk system, time division multiplexing, adc conversion, dac transformation.
shixusuccessful
- 利用VHDL语言，对时分复用通信系统的仿真实现，包括序列产生到序列接收等部分。-Simulation time division multiplexing communication system
fuyong
- 四路四bit时分复用复接器设计，完成拨码开关式输入的复接器。-Four-four time division multiplexing bit multiplexer designed to complete the DIP switch inputs of the multiplexer.
count
- 用Vrilog实现了一个计数器，并用七段数码管进行显示，运用了时分复用，代码简单明了，适合基础学习。-Using Verilog to achieve a counter, the code is simple and clear, suitable for basic learning.
TDM
- 利用时分复用技术将并行输入的四路八位二进制码的信号变成一路信号串行输出(TDM digital multiplex VHDL)