这篇文章讲述了register retiming技术.这项技术是设计VLSI必须要掌握的技能，另外在基于FPGA设计中，register retiming可以使系统频率上升，提高吞吐量。-This paper describe a register retiming mode for VLSI and FPGA-based design. This mode adopted for design can enhance system throughput and increase system

整个系统是一个较为复杂的实时多任务控制系统，合理的任务划分对系统的运行效率、实时性和吞吐量有较大影响。若使任务划分过细，会使任务过于频繁切换，从而增加系统开销。而任务分解不够彻底会影响系统运行的并行性。-The whole system is a more complex real-time multi-task control system, a reasonable division of tasks running on the system s efficiency, timelines