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asynch_fifo
- FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用
mclk
- 基于多时钟的处理，在跨时钟域的处理上有优势-Based on Multi-clock processing, the cross-clock domain processing advantages
asynchronoussignal
- 描述跨时钟域分析,分析和解决异步时钟同步设计问题.-Descr iption of cross-clock domain analysis, analyze and solve design problems in asynchronous clock synchronization.
multiclock_whitepaper
- ASIC中多时钟域处理方法白皮书。描述了ASIC设计/FPGA设计中跨时钟域信号的处理方法。-ASIC in the multi-clock domain approach the White Paper. Describes the ASIC design/FPGA design in the inter-clock domain signal processing methods.
syn_clk
- 一种跨时钟域的时钟同步方法，包含源文件和测试文件~-A cross-clock domain clock synchronization methods, including the source files and test files ~
FPGA_FIFO
- FPGA中同步FIFO的使用小结，FPGA中的FIFO，分为同步FIFO，异步FIFO和双向FIFO。同步FIFO一般用于数据的缓存，异步FIFO一般用于跨时钟域的同步上。-FPGA use in synchronous FIFO summary, FPGA' s FIFO, divided into synchronous FIFO, Asynchronous FIFO and two-way FIFO. Generally used for data synchronization b
FIFOverilog
- 在FPGA进行数据的缓存，在跨时钟域应用较为广泛-Data cache, in the widely used cross-clock domain
hand_shake
- 握手程序，可以完美实现跨时钟域的数据传输-handshake and testbench，verilog HDL
out-limited
- 今天在小熊有人说CSxx下载要扣分，其实我更纠结的是要登录，所以发出写好了N久的东东，简单的说下原理： 比如： 那么通过javascr ipt可以实现获取软件下载以及跳转到下载地址等。 写了个简单的页面，可以得到下载地址，包含扣分的，请用IE本地打开，因为用到了AJAX（本地打开才能跨域），代码如下：-Bear was CSxx download to the offense, I am even more tangled To log in, so to issue writ
FPGA-FIFO
- FPGA-跨时钟域总线信号可靠传输异步FIFO技术安全可靠，格雷码计数，减少亚稳态-FPGA-clock domain crossing bus signals reliable transmission of asynchronous FIFO safe and reliable, Gray code count, reducing the metastable
pulse_syn
- 跨异步时钟域单bit处理模式，工程实际应用中，非常有效。-Cross-domain single-bit processing asynchronous clock mode, practical application of engineering, is very effective.
asyn-fifo
- 功能就是一个FIFO，first in first out！避免跨时钟域的亚稳态-Function is a FIFO, first in first out! To avoid the cross clock domain metastable
AsynCFIFO
- 跨时钟域，异步的FIFO，利用指针移动，数据不移动，通过两级锁存消除跨时钟域的信号竞争-Cross clock domains and asynchronous FIFO, use the pointer to move, do not move the data, eliminating cross clock domain signal through a two-stage competition latch
CrossClockDomain
- 跨时钟域设计不错的设计，进过modelsim仿真通过。-Cross-clock domain design is good design been to modelsim simulation through.
新建 WinRAR ZIP 压缩文件
- 实现跨时钟域数据传输的异步fifo，和i2c总线控制器。(Asynchronous FIFO and I2C bus controller for cross clock domain data transmission.)