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V型机LCD程序2005-11-5
- V型机LCD程序2005-11-5,V型机LCD程序2005-11-5-V-LCD procedures 2005-11-5, V-type LCD procedures 2005-11-5
DPLL0227+V+qt6
- 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
OWA V-9918,MCU89c51程序
- OWA V-9918,MCU89c51程序
EEPROM_RD_WR.rar
- 本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
license
- FreeScale CodeWarrior for PowerPC V 8.8 License
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation
AT070TN83V11
- 群创7寸AT070TN83 V.1 液晶屏PDF详细资料-AT070TN83 V.1
V-f_2
- A New Induction Motor V/f Control Method Capable of High-Performance Regulation at Low Speeds
SiRFatlasV-Datasheet
- CSR/Sirf Atlas V, GPS/PND方案, ARM1136+DSP双核处理器-CSR/Sirf Atlas V, for GPS/PND, ARM1136 with GPS Baseband processor
sgs32
- Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable d
TELECOM3
- This file contains program files associated with the paper titled "Viterbi Implementation on the TMS320C5x for V.32 Modems", Telecom Applications With The TMS320C5x DSPs, Application Book, 1994, SPRA033.
usb_lcd
- A simple V-USB data communication example, intend to display the messages transfered by PC via USB port on a text LCD with a ATmega8. AVR firmware is built with WinAVR GCC and software is built with BC++B5.
clock
- verilog program for real time clock.. select the .v file to view the code.
DM9000A
- DM9000的驱动与逻辑，SOPC可用，内含.V文件-DM9000 driver and logic, SOPC available, containing. V file
Pc.v
- 计算机中每一条机器指令的执行，都离不开程序计数器的正确执行，本程序实现程序计数器。-Computer implementation of each machine instruction, are inseparable from the correct implementation of the program counter, this program achieve the program counter.
V-f_43
- A New Induction Motor V/f Control Method Capable of High-Performance Regulation at Low Speeds
V-f_1
- A New Induction Motor V/f Control Method Capable of High-Performance Regulation at Low Speeds
V-f_3
- A New Induction Motor V/f Control Method Capable of High-Performance Regulation at Low Speedsgf
V35interface-communicate
- V.35接口与E1接口之间转换的基本原理,介绍了E1信道分时隙通信的基本过程，叙述了基于FPGA用VHDL和QuartusII来仿真本系统设计与实现的过程。-V.35 interface and E1 interface to convert between the basic principles of E1 channel introduces the basic process of communication sub-time slot, described by VHDL and FP
motor-v
- 直流电机测速+中文液晶显示，proteus的，完整ok-motor-v,chinese display