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AES256-XILINX10.1
- 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
aes
- 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
AES_cs
- In cryptography, the Advanced Encryption Standard (AES) is a symmetric-key encryption standard adopted by the U.S. government. The standard comprises three block ciphers, AES-128, AES-192 and AES-256, adopted from a larger collection originally publi
aes_core.tar
- 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
FPGA--AES-algorithm
- 本文介绍了AES 数据加密结构, 以及相关的有限域的知识及简单运算, 提出了一种用FPGA 高速实现AES 算法的方案, 该方 案设计的加密模块支持AES 标准的三种密钥长度: 128,192,256, 支持ECB, CBC, CTR 三种工作模式, 即支持feedback 和non- feedback 两种模式, 最后给出了本设计的性能指标-This article describes the AES data encryption structure, as well as the
AES_verilog
- 对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
aes
- 256 bit AES encryption
aes
- AES128/196/256 加解密源码，可实现ECB模式加密，HEX输出。密码及明文没有补齐功能，需手动补齐。无需特殊库文件，适合单片机使用。已测试，可正常使用。-AES128/196/256 encryption source code, can achieve ECB mode encryption, HEX output. The password and the plaintext without the need to manually fill up function. No sp
STM32AES
- 基于STM32F103实现AES算法的工程，支持128,196,256位AES(Based on STM32F103, AES algorithm is implemented, supporting 128196256 bit AES.)