搜索资源列表
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
APB
- It s the verilog source code for AMBA APB 2.0 Slave
a_vhdl_8253_timer_latest.tar
- 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
ahbapb
- AMBA2.0标准的AHB2APb桥，代码通过验证-AMBA2.0 standard AHB2APb Bridge, through the verification code
apb2ahb
- verilog code for apb to ahb convert
au
- 基于APB总线的uart控制器，包括源码和vcs脚本-UART controller based on AMBA APB
I2C
- iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现-iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation
ahb2apb
- Verilog实现的AHB2APB bridge代码-Verilog code to achieve the AHB2APB bridge
code
- 用system verilog 描述的APB总线验证源码，可以用于学习system verilog的使用。-System Verilog descr iption APB bus test source code, can be used to study the use of system Verilog
Actel_DirectCore_CORESPI_4.2.116
- Actel DirectCore CORESPI 4.2.116 Verilog and VHDL RTL source files for SPI controller on APB
APB_slave
- APB slave template for AMBA bus written in Verilog
interrupt_controller
- 中断控制器电路verilog实现源代码,silicon验证的.-interrupt controller IP source code, APB interface.
apbtoaes128_latest.tar
- AES加密算法verilog代码实现，基于APB总线接口数字IP，包含详细的testbench-AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
apbi2c_latest.tar
- APB总线协议转I2C总线协议的接口IP，verilog代码实现，包含详细testbench-APB bus interface to I2C bus interface IP，verilog code
Ahb2Apb
- AHB总线协议转APB总线协议的接口IP，使用Verilog代码实现，有详细的英文注释(AHB bus protocol turn APB bus interface IP, use Verilog code implementation, and have a detailed knowledge of the English comments)
apb.v
- AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
apb
- APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
apb_uart
- 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
24_Timer
- 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
apb_timer.tar
- 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the descr