搜索资源列表
4bits_alu
- 实现4位加减乘除的alu，采用超前进位加法和布斯乘法，代码较为简单。-achieve four of the ALU arithmetic using CLA Bush and multiplication, code more simple.
ADD_SUB
- 11,13,16位超前进位加法器的Verilog HDL源代码。-11,13,16-CLA for the Verilog HDL source code.
DSPlib
- 经典的DSP程序库 -classic DSP library of cla ssic DSP library of classic DSP library
cla_vhd
- 超前进位加法器的例子,包括源码和测试文件,压缩包,无密码.-CLA of examples, including source code and test documents, compressed, without a password.
adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
AVR-CDC.2006-07-18
- 使用avr软件模拟usb，并实现cdc cla-use avr usb simulation software, and achieve cdc cla
wince
- See Hanoi.cpp for the implementation of this cla
CLA
- microSD卡资料.开发可以参考。
16bit-CLA
- 16 bit carry look ahead adder verilog code
5
- simple code based on verilog shifter , cla ,clg , ALU ,PC, decoder , tb_top
adder_32
- 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
4
- Verilog写的 8 位超前进位加法器-Verilog write 8-bit CLA
CLA.VHDL.CODE
- cla vhdl code with a picture files.
ADDER(2)
- simple 16-bet CLA adder
jiafaqi
- Verilog 16位超前进位加法器源码-Verilog 16 bit CLA source
4
- simple code based on verilog shifter , cla ,clg , ALU , PC
cla-adder
- cla adder code in vhdl
CLA-CCSv3.3
- F28035的DSP，CCS3.3应用环境的配置，可以在一台电脑上同时打开主CPU和CLA的调试界面，对于使用CLA的并且不习惯使用新版ccs4开发环境的用户很有用！-F28035 the DSP, CCS3.3 application environment configuration on a computer at the same time open the main CPU and CLA debug interface, users not accustomed to using n
CLA-CCSv4.x
- F28035DSP，在CCS4环境下的配置，可以同时调试主CPU和CLA-F28035DSP, in the environment of CCS4 configuration, can debug the main CPU and CLA